SPDIF receiver interface (SPDIFRX) RM0390
916/1328 RM0390 Rev 4
A simple way to check if valid data are available into the SPDIFRX_IN line is to switch the
SPDIFRX into the STATE_SYNC, with bit WFA set to 1. The description hereafter will focus
on detection. It is also possible to implement this function as follow:
• The software has to check from time to time (i.e. every 100 ms for example) if the
SPDIFRX can find synchronization. This can be done by checking if the bit TERR is
set. When it is set it indicates that no activity as been found.
• Connect the SPDIFRX_IN input to an external interrupt event block in order to detect
transitions of SPDIFRX_IN line. When activity is detected, then SPDIFRXEN can be
set to 0b01 or 0b11.
For those two implementations, the bit WFA is set to 0.
27.4.1 Initialization phase
• The initialization function will look like this:
• Configure the DMA transfer for both audio samples and IEC60958 channel status and
user information (DMA channel selection and activation, priority, number of data to
transfer, circular/no circular mode, DMA interrupts)
• Configure the destination address:
– Configure the address of the SPDIFRX_CSR register as source address for
IEC60958 channel status and user information
– Configure the address of the SPDIFRX_DR register as source address for audio
samples
– Enable the generation of the SPDIFRX_CLK. Refer to Table 168 in order to define
the minimum clock frequency versus supported audio sampling rate.
Note that the audio sampling rate of the received stream is not known in advance.
This means that the user has to select a SPDIFRX_CLK frequency at least 704
times higher than the maximum audio sampling rate the application is supposed to
handle: for example if the application is able to handle streams to up to 96 kHz,
then F
SPDIFRX_CLK
shall be at least 704 x 96 kHz = 67.6 MHz
• Enable interrupt for errors and event signaling (IFEIE = SYNCDIE = OVRIE, PERRIE =
1, others set to 0). Note that SYNCDIE can be set to 0.
• Configure the SPDIFRX_CR register:
– INSEL shall select the wanted input
– NBTR = 2, WFA = 1 (16 re-tries allowed, wait for activity before going to
synchronization phase),
– PTMSK = CUMSK = 1 (Preamble, C and U bits are not mixed with data)
– VMSK = PMSK = 0 (Parity error and validity bit mixed with data)
– CHSEL = 0 (channels status will be read from sub-frame A)
– DRFMT = 0b01 (data aligned to the left)
– RXSTEO = 1 (expected stereo mode linear)
– CBDMAEN = RXDMAEN = 1 (enable DMA channels)
– SPDIFRXEN = 0b01 (switch SPDIFRX to STATE_SYNC)
• The CPU can enter in WFI mode
Then the CPU will receive interrupts coming either from DMA or SPDIFRX.
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