RM0390 Rev 4 1235/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
3. The OTG_HS host attempts to send an IN token at the beginning of the next (odd)
frame/micro-frame.
4. As soon the packet is received and written to the receive FIFO, the OTG_HS host
generates a CHH interrupt.
5. In response to the CHH interrupt, reinitialize the channel for the next transfer.
Figure 423. Normal isochronous IN transactions - DMA mode
• Bulk and control OUT/SETUP split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
1. Initialize and enable channel x for start split as explained in Section : Channel
initialization.
2. The OTG_HS host starts fetching the first packet as soon the channel is enabled and
writes the OUT request along with the last 32-bit word fetch.
3. After successfully transmitting start split, the OTG_HS host generates the CHH
interrupt.
4. In response to the CHH interrupt, set the COMPLSPLT bit in OTG_HCSPLT1 to send
the complete split.
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