RM0390 Rev 4 377/1328
RM0390 Analog-to-digital converter (ADC)
400
first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM,
then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM.
The sequence is the following:
• 1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
• 2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]
• 3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]
• 4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...
Figure 85. Interleaved mode on 1 channel in continuous conversion mode: triple ADC
mode
13.9.4 Alternate trigger mode
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of ADC1.
Note: Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.
Dual ADC mode
• When the 1st trigger occurs, all injected ADC1 channels in the group are converted
• When the 2nd trigger occurs, all injected ADC2 channels in the group are converted
• and so on
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group
have been converted.
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