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Digital-to-analog converter (DAC) RM0390

418/1328 RM0390 Rev 4

14.5.6 DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2)

Address offset: 0x14

Reset value: 0x0000 0000

14.5.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)

Address offset: 0x18

Reset value: 0x0000 0000

14.5.8 DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2)

Address offset: 0x1C

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. DACC2DHR[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data

These bits are written by software which specifies 12-bit data for DAC channel2.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

DACC2DHR[11:0] Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data

These bits are written by software which specify 12-bit data for DAC channel2.

Bits 3:0 Reserved, must be kept at reset value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0]

rw rw rw rw rw rw rw rw

ST STM32F446 Series User Manual

Other manuals for ST STM32F446 Series