Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390
700/1328 RM0390 Rev 4
Figure 244. FMPI2C initialization flowchart
23.4.5 Software reset
A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In
that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. FMPI2C_CR2 register: START, STOP, NACK
2. FMPI2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF,
BERR, ARLO, OVR
and in addition when the SMBus feature is supported:
1. FMPI2C_CR2 register: PECBYTE
2. FMPI2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least 3 APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence: - Write PE=0 - Check
PE=0 - Write PE=1.
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&OHDU3(ELWLQ)03,&B&5
,QLWLDOVHWWLQJV
&RQILJXUH$1)2))DQG'1)>@LQ
)03,&B&5
&RQILJXUH35(6&>@
6'$'(/>@6&/'(/>@6&/+>@
6&//>@LQ)03,&B7,0,1*5
&RQILJXUH12675(7&+LQ)03,&B&5
6HW3(ELWLQ)03,&B&5
(QG
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