HDMI-CEC controller (HDMI-CEC) RM0390
1274/1328 RM0390 Rev 4
32.6 HDMI-CEC interrupts
An interrupt can be produced:
• during reception if a Receive Block Transfer is finished or if a Receive Error occurs.
• during transmission if a Transmit Block Transfer is finished or if a Transmit Error
occurs.
T
n0
x1.5
The nominal time a device is permitted return to a
high impedance state (logical 0).
T
4
01.7
The latest time a device is permitted return to a high
impedance state (logical 0).
11.8
T
5
11.85
The earliest time for the start of a following bit.
02.05
T
nf
x 2.4 The nominal data bit period.
T
6
02.75
The latest time for the start of a following bit.
12.95
Table 234. TXERR timing parameters (continued)
Time RXTOL ms Description
Table 235. HDMI-CEC interrupts
Interrupt event Event flag Enable Control bit
Rx-Byte Received
RXBR RXBRIE
End of reception
RXEND RXENDIE
Rx-Overrun
RXOVR RXOVRIE
RxBit Rising Error
BRE BREIE
Rx-Short Bit Period Error
SBPE SBPEIE
Rx-Long Bit Period Error
LBPE LBPEIE
Rx-Missing Acknowledge Error
RXACKE RXACKEIE
Arbitration lost
ARBLST ARBLSTIE
Tx-Byte Request
TXBR TXBRIE
End of transmission
TXEND TXENDIE
Tx-Buffer Underrun
TXUDR TXUDRIE
Tx-Error
TXERR TXERRIE
Tx-Missing Acknowledge Error
TXACKE TXACKEIE
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