RM0390 Rev 4 1183/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
31.15.55 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx)
(x = 0..5[FS] /8[HS], where x = Endpoint number)
Address offset: 0xB08 + (x * 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in Figure 409. The application must read this register when the OUT
endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set.
Before the application can read this register, it must first read the OTG_DAINT register to
get the exact endpoint number for the OTG_DOEPINTx
register. The application must clear
the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and
OTG_GINTSTS registers.
Note: Configuration register for USB OTG FS.
Bit 17 NAKSTS: NAK status
Indicates the following:
0: The core is transmitting non-NAK handshakes based on the FIFO status.
1: The core is transmitting NAK handshakes on this endpoint.
When either the application or the core sets this bit, the core stops receiving data, even if
there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit’s
setting, the core always responds to SETUP data packets with an ACK handshake.
Bit 16 Reserved, must be kept at reset value.
Bit 15 USBAEP: USB active endpoint
This bit is always set to 1, indicating that a control endpoint 0 is always active in all
configurations and interfaces.
Bits 14:2 Reserved, must be kept at reset value.
Bits 1:0 MPSIZ[1:0]: Maximum packet size
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in
control IN endpoint 0.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. NYET NAK BERR Res. Res. Res.
OUT
PKT
ERR
Res. Res.
STSPH
SRX
OTEP
DIS
STUP Res.
EP
DISD
XFRC
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