RM0390 Rev 4 917/1328
RM0390 SPDIF receiver interface (SPDIFRX)
929
27.4.2 Handling of interrupts coming from SPDIFRX
When an interrupt from the SPDIFRX is received, then the software has to check what is the
source of the interrupt by reading the SPDIFRX_SR register.
• If SYNCD is set to 1, then it means that the synchronization has been properly
completed. No action has to be performed in our case as the DMA is already
programmed. The software just needs to wait for DMA interrupt in order to read
channel status information.
The SYNCD flag must be cleared by setting SYNCDCF bit of SPDIFRX_IFCR register
to 1.
• If TERR or SERR or FERR are set to 1, the software has to set SPDIFRXEN to 0, and
re-start from the initialization phase.
– TERR indicates that a time-out occurs either during synchronization phase or
after.
– SERR indicates that the synchronization fails because the maximum allowed re-
tries have been reached.
– FERR indicates that the reading of information after synchronization fails
(unexpected preamble, bad data decoding...).
• If PERR is set to 1, it means that a parity error has been detected, so one of the
received audio sample or the channel status or user data bits are corrupted. The action
taken here depends on the application: one action could be to drop the current channel
status block as it is not reliable. There is no need to re-start from the initialization
phase, as the synchronization is not lost.
The PERR flag must be cleared by setting PERRCF bit of SPDIFRX_IFCR register
to 1.
27.4.3 Handling of interrupts coming from DMA
If an interrupt is coming from the DMA channel used of the channel status (SPDIFRX_CSR):
If no error occurred (i.e. PERR), the CPU can start the decoding of channel information.
For example bit 1 of the channel status informs the user if the current stream is linear or
not. This information is very important in order to set-up the proper processing chain. In
the same way, bits 24 to 27 of the channel status give the sampling frequency of the
stream incoming stream.
Thanks to that information, the user can then configure the RXSTEO bit and DRFMT
field prior to start the data reception. For example if the current stream is non linear
PCM then RXSTEO is set to 0, and DRFMT is set to 0b10. Then the user can enable
the data reception by setting SPDIFRXEN to 0b11.
The bit SOB, when set to 1 indicates the start of a new block. This information will help
the software to identify the bit 0 of the channel status. Note that if the DMA generates
an interrupt every time 24 values are transferred into the memory, then the first word
will always correspond to the start of a new block.
If an interrupt is coming from the DMA channel used of the audio samples (SPDIFRX_DR):
The process performed here depends of the data type (linear or non-linear), and on the
data format selected.
For example in linear mode, if PE or V bit is set a special processing can be performed
locally in order to avoid spurs on output. In non-linear mode those bits are not important
as data frame have their own checksum.
To Next Page
Loading...
Need help?
General
