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Interrupts and events RM0390

248/1328 RM0390 Rev 4

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.

If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,

the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration,

both generate a trigger condition.

10.3.5 Software interrupt event register (EXTI_SWIER)

Address offset: 0x10

Reset value: 0x0000 0000

10.3.6 Pending register (EXTI_PR)

Address offset: 0x14

Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res.

SWIER

rw rw rw rw rw rw rw

1514131211109 8 7654321 0

SWIER

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx: Software Interrupt on line x

If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is

set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an

interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. PR22 PR21 PR20 PR19 PR18 PR17 PR16

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

1514131211109 8 7654321 0

PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PRx: Pending bit on line x

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to ‘1’.

ST STM32F446 Series User Manual

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