RM0390 Rev 4 1175/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
Note: Configuration register applies only to USB OTG FS
31.15.48 OTG device IN endpoint x control register (OTG_DIEPCTLx)
(x = 1..5[FS] / 0..8[HS], where x = endpoint number)
Address offset: 0x900 + (x * 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
Bit 15 USBAEP: USB active endpoint
This bit is always set to 1, indicating that control endpoint 0 is always active in all
configurations and interfaces.
Bits 14:2 Reserved, must be kept at reset value.
Bits 1:0 MPSIZ[1:0]: Maximum packet size
The application must program this field with the maximum packet size for the current logical
endpoint.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA EPDIS
SODD
FRM
SD0
PID/
SEVN
FRM
SNAK CNAK TXFNUM[3:0] STALL Res. EPTYP[1:0]
NAK
STS
EO
NUM/
DPID
rs rs w w w w rw rw rw rw rw/rs rw rw r r
1514131211109876543210
USBA
EP
Res. Res. Res. Res. MPSIZ[10:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 EPENA: Endpoint enable
The application sets this bit to start transmitting data on an endpoint.
The core clears this bit before setting any of the following interrupts on this endpoint:
– SETUP phase done
– Endpoint disabled
– Transfer completed
Bit 30 EPDIS: Endpoint disable
The application sets this bit to stop transmitting/receiving data on an endpoint, even before
the transfer for that endpoint is complete. The application must wait for the endpoint
disabled interrupt before treating the endpoint as disabled. The core clears this bit before
setting the endpoint disabled interrupt. The application must set this bit only if endpoint
enable is already set for this endpoint.
Bit 29 SODDFRM: Set odd frame
Applies to isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd frame (EONUM) field to odd frame.
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