USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1186/1328 RM0390 Rev 4
31.15.57 OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx)
(x = 0..8, where x = endpoint number)
Address offset: 0xB14 + (x * 0x20)
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
Bit 31 Reserved, must be kept at reset value.
Bits 30:29 STUPCNT[1:0]: SETUP packet count
This field specifies the number of back-to-back SETUP data packets the endpoint can
receive.
01: 1 packet
10: 2 packets
11: 3 packets
Bits 28:20 Reserved, must be kept at reset value.
Bit 19 PKTCNT: Packet count
This field is decremented to zero after a packet is written into the Rx FIFO.
Bits 18:7 Reserved, must be kept at reset value.
Bits 6:0 XFRSIZ[6:0]: Transfer size
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only
after it has exhausted the transfer size amount of data. The transfer size can be set to the
maximum packet size of the endpoint, to be interrupted at the end of each packet.
The core decrements this field every time a packet is read from the Rx FIFO and written to
the external memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
DMAADDR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 DMAADDR[31:0]: DMA Address
This field holds the start address in the external memory from which the data for the
endpoint must be fetched. This register is incremented on every AHB transaction.
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