Direct memory access controller (DMA) RM0390
220/1328 RM0390 Rev 4
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the
corresponding stream is set in the status register to indicate the DMA completion. To
know the number of data items transferred during the DMA transfer, read the
DMA_SxNDTR register and apply the following formula:
– Number_of_data_transferred = 0xFFFF – DMA_SxNDTR
• Normal stream interruption due to the reception of a last data hardware signal: the
stream is automatically interrupted when the peripheral requests the last transfer
(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding
stream is set in the status register to indicate the DMA transfer completion. To know the
number of data items transferred, read the DMA_SxNDTR register and apply the same
formula as above.
• The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is
set in the status register to indicate the forced DMA transfer completion. The stream is
automatically switched off even though the last data hardware signal (single or burst)
has not been yet asserted. The already transferred data is not lost. This means that a
maximum of 65535 data items can be managed by the DMA in a single transaction,
even in peripheral flow control mode.
Note: When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The circular mode is forbidden in the peripheral flow controller mode.
9.3.17 Summary of the possible DMA configurations
Table 35 summarizes the different possible DMA configurations. The forbidden
configurations are highlighted in gray in the table.
Table 35. Possible DMA configurations
DMA transfer
mode
Source Destination
Flow
controller
Circular
mode
Transfer
type
Direct
mode
Double-
buffer mode
Peripheral-to-
memory
AHB
peripheral port
AHB
memory port
DMA Possible
single Possible
Possible
burst
Forbidden
Peripheral
Forbidden
single Possible
Forbidden
burst
Forbidden
Memory-to-
peripheral
AHB
memory port
AHB
peripheral port
DMA Possible
single Possible
Possible
burst Forbidden
Peripheral
Forbidden
single Possible
Forbidden
burst Forbidden
Memory-to-
memory
AHB
peripheral port
AHB
memory port
DMA only
Forbidden
single
Forbidden Forbidden
burst
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