Analog-to-digital converter (ADC) RM0390
362/1328 RM0390 Rev 4
Figure 73. Timing diagram
13.3.8 Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 85 shows how the ADC_CR1 register should be configured to enable the analog
watchdog on one or more channels.
Figure 74. Analog watchdog’s guarded area
!$#?#,+
%/#
.EXT!$#CONVERSION
!$#CONVERSION
#ONVERSIONTIME
T
34!"
!$#
3OFTWARECLEARSTHE%/#BIT
TOTALCONVTIME
3TARTSTCONVERSION 3TARTNEXTCONVERSION
AIB
!$/.
3734!24
*3734!24
Table 85. Analog watchdog channel selection
Channels guarded by the analog
watchdog
ADC_CR1 register control bits (x = don’t care)
AWDSGL bit AWDEN bit JAWDEN bit
None x 0 0
All injected channels 0 0 1
DL
$QDORJYROWDJH
+LJKHUWKUHVKROG
/RZHUWKUHVKROG
*XDUGHGDUHD
+75
/75
To Next Page
Loading...
Need help?
General
