Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390
868/1328 RM0390 Rev 4
has to be reset between sessions by the SPI disable sequence by re-enabling the CRCEN
bit described above at both master and slave sides, else the CRC calculation can be
corrupted at this specific mode.
26.5 SPI interrupts
During SPI communication an interrupts can be generated by the following events:
• Transmit Tx buffer ready to be loaded
• Data received in Rx buffer
• Master mode fault
• Overrun error
• TI frame format error
Interrupts can be enabled and disabled separately.
Table 163. SPI interrupt requests
Interrupt event Event flag Enable Control bit
Transmit Tx buffer ready to be loaded TXE TXEIE
Data received in Rx buffer RXNE RXNEIE
Master Mode fault event MODF
ERRIE
Overrun error OVR
CRC error CRCERR
TI frame format error FRE
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