RM0390 Rev 4 423/1328
RM0390 Digital camera interface (DCMI)
448
15 Digital camera interface (DCMI)
15.1 DCMI introduction
The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black & white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing like resizing is performed in the camera module.
This interface is also able to transmit a parallel data flow, allowing it to emulate a camera
module interfacing with another camera interface.
It may also be used as a generic synchronous parallel interface ensuring a high data rate
transfer, in receive or in transmit mode. It is a slave interface, the external clock and data
flow control being ensured externally (by another device or by other resources of the
STM32, e.g. timers).
15.2 DCMI main features
• 8-, 10-, 12- or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14- bit progressive video: either monochrome or raw bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG
15.3 DCMI clocks
The digital camera interface uses two clock domains, DCMI_PIXCLK and HCLK. The
signals generated with DCMI_PIXCLK are sampled on the rising edge of HCLK once they
are stable. An enable signal is generated in the HCLK domain, to indicate that data coming
from the camera are stable and can be sampled. The maximum DCMI_PIXCLK period must
be higher than 2.5 HCLK periods.
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