RM0390 Rev 4 1171/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
31.15.45 OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1)
Address offset: 0x844
Reset value: 0x0000 0000
This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt
OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the
OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this
register. Status bits are masked by default.
Note: Configuration register applies only to USB OTG HS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. NAKM Res. Res. Res. Res.
TXFU
RM
Res.
INEPN
EM
Res.
ITTXFE
MSK
TOM
AHB
ERRM
EPDM
XFRC
M
rw rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAKM: NAK interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 TXFURM: FIFO underrun mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 Reserved, must be kept at reset value.
Bit 6 INEPNEM: IN endpoint NAK effective mask
0: Masked interrupt
1: Unmasked interrupt
Bit 5 Reserved, must be kept at reset value.
Bit 4 ITTXFEMSK: IN token received when Tx FIFO empty mask
0: Masked interrupt
1: Unmasked interrupt
Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints)
0: Masked interrupt
1: Unmasked interrupt
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