RM0390 Rev 4 695/1328
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
758
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 23.3: FMPI2C implementation.
23.4.2 FMPI2C clock requirements
The FMPI2C kernel is clocked by FMPI2CCLK.
The FMPI2CCLK period t
I2CCLK
must respect the following conditions:
t
I2CCLK
< (t
LOW
- t
filters
) / 4 and t
I2CCLK
< t
HIGH
with:
t
LOW
: SCL low time and t
HIGH
: SCL high time
t
filters:
when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
I2CCLK
.
The PCLK clock period t
PCLK
must respect the following condition:
t
PCLK
< 4/3 t
SCL
with t
SCL
: SCL period
Caution: When the FMPI2C kernel is clocked by PCLK, this clock must respect the conditions for
t
I2CCLK
.
23.4.3 Mode selection
The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the FMPI2C interface initiates a data transfer and generates the clock
signal. A serial data transfer always begins with a START condition and ends with a STOP
condition. Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection can be enabled or disabled
by software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.
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