USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1108/1328 RM0390 Rev 4
Device-mode CSR map
These registers must be programmed every time the core changes to device mode.
Table 225. Device-mode control and status registers
Acronym
Offset
address
Register name
OTG_DCFG 0x800 Section 31.15.32: OTG device configuration register (OTG_DCFG)
OTG_DCTL 0x804 Section 31.15.33: OTG device control register (OTG_DCTL)
OTG_DSTS 0x808 Section 31.15.34: OTG device status register (OTG_DSTS)
OTG_DIEPMSK 0x810
Section 31.15.35: OTG device IN endpoint common interrupt mask
register (OTG_DIEPMSK)
OTG_DOEPMSK 0x814
Section 31.15.36: OTG device OUT endpoint common interrupt mask
register (OTG_DOEPMSK)
OTG_DAINT 0x818
Section 31.15.37: OTG device all endpoints interrupt register
(OTG_DAINT)
OTG_DAINTMSK 0x81C
Section 31.15.38: OTG all endpoints interrupt mask register
(OTG_DAINTMSK)
OTG_DVBUSDIS 0x828
Section 31.15.39: OTG device VBUS discharge time register
(OTG_DVBUSDIS)
OTG_DVBUSPULSE 0x82C
Section 31.15.40: OTG device VBUS pulsing time register
(OTG_DVBUSPULSE)
OTG_DTHRCTL 0x830
Section 31.15.41: OTG device threshold control register
(OTG_DTHRCTL)
OTG_DIEPEMPMSK 0x834
Section 31.15.42: OTG device IN endpoint FIFO empty interrupt mask
register (OTG_DIEPEMPMSK)
OTG_DEACHINT 0x838
Section 31.15.43: OTG device each endpoint interrupt register
(OTG_DEACHINT)
OTG_DEACHINTMSK 0x83C
Section 31.15.44: OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK)
OTG_HS_DIEPEACHM
SK1
0x844
Section 31.15.45: OTG device each IN endpoint-1 interrupt mask
register (OTG_HS_DIEPEACHMSK1)
OTG_HS_DOEPEACHM
SK1
0x884
Section 31.15.46: OTG device each OUT endpoint-1 interrupt mask
register (OTG_HS_DOEPEACHMSK1)
OTG_DIEPCTL0 0x900
Section 31.15.47: OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) for USB_OTG FS
OTG_DIEPCTLx
0x920
0x940
...
0x9A0
Section 31.15.48: OTG device IN endpoint x control register
(OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint number)
for USB_OTG FS
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