EasyManuals Logo

ST STM32F446 Series User Manual

ST STM32F446 Series
1328 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #897 background imageLoading...
Page #897 background image
RM0390 Rev 4 897/1328
RM0390 SPDIF receiver interface (SPDIFRX)
929
27 SPDIF receiver interface (SPDIFRX)
27.1 SPDIFRX interface introduction
The SPDIFRX interface handles S/PDIF audio protocol.
27.2 SPDIFRX main features
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
SOPDs B, M and W insertion inside S/PDIF flow
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
27.3 SPDIFRX functional description
The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS.
The receiver provides all the necessary features to detect the symbol rate, and decode the
incoming data. It is possible to use a dedicated path for the user and channel information in
order to ease the interface handling. Figure 338 shows a simplified block diagram.
The SPDIFRX_DC block is responsible of the decoding of the S/PDIF stream received from
SPDIFRX_IN[4:1] inputs. This block re-sample the incoming signal, decode the manchester
stream, recognize frames, sub-frames and blocks elements. It delivers to the REG_IF part,
decoded data, and associated status flags.
This peripheral can be fully controlled via the APB1 bus, and can handle two DMA channels:
A DMA channel dedicated to the transfer of audio samples
A DMA channel dedicated to the transfer of IEC60958 channel status and user
information
Interrupt services are also available either as an alternative function to the DMA, or for
signaling error or key status of the peripheral.
The SPDIFRX also offers a signal named spdifrx_frame_sync, which toggles every time
that a sub-frame’s preamble is detected. So the duty cycle will be 50%, and the frequency
equal to the frame rate.
This signal can be connected to timer events, in order to compute frequency drift.

Table of Contents

Other manuals for ST STM32F446 Series

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F446 Series and is the answer not in the manual?

ST STM32F446 Series Specifications

General IconGeneral
BrandST
ModelSTM32F446 Series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals