RM0390 Rev 4 443/1328
RM0390 Digital camera interface (DCMI)
448
15.7.6 DCMI interrupt clear register (DCMI_ICR)
Address offset: 0x14
Reset value: 0x0000 0000
The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the
corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LINE
_ISC
VSYNC
_ISC
ERR
_ISC
OVR
_ISC
FRAME
_ISC
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Bits 31:5 Reserved, must be kept at reset value.
Bit 4 LINE_ISC: line interrupt status clear
Writing a ‘1’ into this bit clears LINE_RIS in the DCMI_RIS register
Bit 3 VSYNC_ISC: Vertical Synchronization interrupt status clear
Writing a ‘1’ into this bit clears the VSYNC_RIS bit in DCMI_RIS
Bit 2 ERR_ISC: Synchronization error interrupt status clear
Writing a ‘1’ into this bit clears the ERR_RIS bit in DCMI_RIS
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_ISC: Overrun interrupt status clear
Writing a ‘1’ into this bit clears the OVR_RIS bit in DCMI_RIS
Bit 0 FRAME_ISC: Capture complete interrupt status clear
Writing a ‘1’ into this bit clears the FRAME_RIS bit in DCMI_RIS
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