RM0390 Rev 4 1179/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
31.15.50 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0)
Address offset: 0x910
Reset value: 0x0000 0000
The application must modify this register before enabling endpoint 0. Once endpoint 0 is
enabled using the endpoint enable bit in the device control endpoint 0 control registers
(EPENA in OTG_DIEPCTL0), the core modifies this register. The application can only read
this register once the core has cleared the endpoint enable bit.
Nonzero endpoints use the registers for endpoints 1–3.
Bit 3 TOC: Timeout condition
Indicates that the core has detected a timeout condition on the USB for the last IN token on
this endpoint.
Bit 2 AHBERR: AHB error for USB OTG HS
This is generated only in internal DMA mode when there is an AHB error during an AHB
read/write. The application can read the corresponding endpoint DMA address register to
get the error address.
Bit 1 EPDISD: Endpoint disabled interrupt
This bit indicates that the endpoint is disabled per the application’s request.
Bit 0 XFRC: Transfer completed interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the
USB, for this endpoint.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKTCNT[1:0] Res. Res. Res.
rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. XFRSIZ[6:0]
rw rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:19 PKTCNT[1:0]: Packet count
Indicates the total number of USB packets that constitute the transfer size amount of data for
endpoint 0.
This field is decremented every time a packet (maximum size or short packet) is read from
the Tx FIFO.
Bits 18:7 Reserved, must be kept at reset value.
Bits 6:0 XFRSIZ[6:0]: Transfer size
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only
after it has exhausted the transfer size amount of data. The transfer size can be set to the
maximum packet size of the endpoint, to be interrupted at the end of each packet.
The core decrements this field every time a packet from the external memory is written to
the Tx FIFO.
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