USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1152/1328 RM0390 Rev 4
31.15.26 OTG host channel x split control register (OTG_HCSPLTx)
(x = 0..15, where x = Channel number)
Address offset: 0x504 + (x * 0x20)
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS.
Bits 21:20 MCNT[1:0]: Multicount
This field indicates to the host the number of transactions that must be executed per frame
for this periodic endpoint. For non-periodic transfers, this field is not used
00: Reserved. This field yields undefined results
01: 1 transaction
10: 2 transactions per frame to be issued for this endpoint
11: 3 transactions per frame to be issued for this endpoint
Note: This field must be set to at least 01.
Bits 19:18 EPTYP[1:0]: Endpoint type
Indicates the transfer type selected.
00: Control
01: Isochronous
10: Bulk
11: Interrupt
Bit 17 LSDEV: Low-speed device
This field is set by the application to indicate that this channel is communicating to a low-
speed device.
Bit 16 Reserved, must be kept at reset value.
Bit 15 EPDIR: Endpoint direction
Indicates whether the transaction is IN or OUT.
0: OUT
1: IN
Bits 14:11 EPNUM[3:0]: Endpoint number
Indicates the endpoint number on the device serving as the data source or sink.
Bits 10:0 MPSIZ[10:0]: Maximum packet size
Indicates the maximum packet size of the associated endpoint.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLIT
EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
COMP
LSPLT
rw
rw
1514131211109876543210
XACTPOS[1:0] HUBADDR[6:0] PRTADDR[6:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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