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Reset and clock control (RCC) RM0390

154/1328 RM0390 Rev 4

6.3.17 RCC AHB3 peripheral clock enable in low power mode register

(RCC_AHB3LPENR)

Address offset: 0x58

Reset value: 0x0000 0003

Access: no wait state, word, half-word and byte access.

6.3.18 RCC APB1 peripheral clock enable in low power mode register

(RCC_APB1LPENR)

Address offset: 0x60

Reset value: 0x3FFF C9FF

Access: no wait state, word, half-word and byte access.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG FS clock disabled during Sleep mode

1: USB OTG FS clock enabled during Sleep mode

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 DCMILPEN: Camera interface enable during Sleep mode

This bit is set and cleared by software.

0: Camera interface clock disabled during Sleep mode

1: Camera interface clock enabled during Sleep mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

QSPI

LPEN

FMC

LPEN

rw rw

Bits 31:2Reserved, must be kept at reset value.

Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode

This bit is set and cleared by software.

0: QUADSPI module clock disabled during Sleep mode

1: QUADSPI module clock enabled during Sleep mode

Bit 0 FMCLPEN: Flexible memory controller module clock enable during Sleep mode

This bit is set and cleared by software.

0: FMC module clock disabled during Sleep mode

1: FMC module clock enabled during Sleep mode

ST STM32F446 Series User Manual

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