RM0390 Rev 4 155/1328
RM0390 Reset and clock control (RCC)
175
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
DAC
LPEN
PWR
LPEN
CECLP
EN
CAN2
LPEN
CAN1
LPEN
FMPI2C1
LPEN
I2C3
LPEN
I2C2
LPEN
I2C1
LPEN
UART5
LPEN
UART4
LPEN
USART3
LPEN
USART2
LPEN
SPDIFRX
LPEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
LPEN
SPI2
LPEN
Res. Res.
WWDG
LPEN
Res. Res.
TIM14
LPEN
TIM13
LPEN
TIM12
LPEN
TIM7
LPEN
TIM6
LPEN
TIM5
LPEN
TIM4
LPEN
TIM3
LPEN
TIM2
LPEN
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACLPEN: DAC interface clock enable during Sleep mode
This bit is set and cleared by software.
0: DAC interface clock disabled during Sleep mode
1: DAC interface clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
This bit is set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 27 CECLPEN: CEC clock enable during Sleep mode
This bit is set and cleared by software.
0: CEC clock disabled during Sleep mode
1: CEC clock enabled during Sleep mode
Bit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode
This bit is set and cleared by software.
0: CAN 2 clock disabled during sleep mode
1: CAN 2 clock enabled during sleep mode
Bit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode
This bit is set and cleared by software.
0: CAN 1 clock disabled during Sleep mode
1: CAN 1 clock enabled during Sleep mode
Bit 24 FMPI2C1LPEN: FMPI2C1 clock enable during Sleep mode
This bit is set and cleared by software.
0: FMPI2C1 clock disabled during Sleep mode
1: FMPI2C1 clock enabled during Sleep mode
Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C3 clock disabled during Sleep mode
1: I2C3 clock enabled during Sleep mode
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C1 clock disabled during Sleep mode
1: I2C1 clock enabled during Sleep mode