RM0390 Rev 4 1185/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
31.15.56 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0)
Address offset: 0xB10
Reset value: 0x0000 0000
The application must modify this register before enabling endpoint 0. Once endpoint 0 is
enabled using the endpoint enable bit in the OTG_DOEPCTL0 registers (EPENA bit in
OTG_DOEPCTL0), the core modifies this register. The application can only read this
register once the core has cleared the endpoint enable bit.
Nonzero endpoints use the registers for endpoints 1–5[FS] /8[HS].
Bit 4 OTEPDIS: OUT token received when endpoint disabled
Applies only to control OUT endpoints.
Indicates that an OUT token was received when the endpoint was not yet enabled. This
interrupt is asserted on the endpoint for which the OUT token was received.
Bit 3 STUP: SETUP phase done
Applies to control OUT endpoint only.
Indicates that the SETUP phase for the control endpoint is complete and no more back-to-
back SETUP packets were received for the current control transfer. On this interrupt, the
application can decode the received SETUP data packet.
Bit 2 AHBERR: AHB error for USB OTG HS
This is generated only in internal DMA mode when there is an AHB error during an AHB
read/write. The application can read the corresponding endpoint DMA address register to
get the error address.
Bit 1 EPDISD: Endpoint disabled interrupt
This bit indicates that the endpoint is disabled per the application’s request.
Bit 0 XFRC: Transfer completed interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the
USB, for this endpoint.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. STUPCNT[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res.
PKTCNT
Res. Res. Res.
rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. XFRSIZ[6:0]
rw rw rw rw rw rw rw
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