ST STM32F446 Series User Manual

RM0390 Rev 4 151/1328
RM0390 Reset and clock control (RCC)
175
6.3.15 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x6067 90FF
Access: no wait state, word, half-word and byte access.
Bit 9 ADC2EN: ADC2 clock enable
This bit is set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock enabled
Bit 8 ADC1EN: ADC1 clock enable
This bit is set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
This bit is set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
Bit 4 USART1EN: USART1 clock enable
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 clock enable
This bit is set and cleared by software.
0: TIM8 clock disabled
1: TIM8 clock enabled
Bit 0 TIM1EN: TIM1 clock enable
This bit is set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
OTGHS
ULPI
LPEN
OTGHS
LPEN
Res. Res. Res. Res. Res. Res.
DMA2
LPEN
DMA1
LPEN
Res. Res.
BKP
SRAM
LPEN
SRAM2
LPEN
SRAM1
LPEN
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITF
LPEN
Res. Res.
CRC
LPEN
Res. Res. Res. Res.
GPIOH
LPEN
GPIOG
LPEN
GPIOF
LPEN
GPIOE
LPEN
GPIOD
LPEN
GPIOC
LPEN
GPIOB
LPEN
GPIOA
LPEN
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ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English