RM0390 Rev 4 1319/1328
RM0390 Revision history
1323
35 Revision history
Table 254. Document revision history
Date Revision Changes
17-Mar-2015 1 Initial release.
12-Jan-2016 2
Updated Section 5.1.2: Battery backup domain.
Updated Table 19: Standby mode entry and exit.
Updated Section 6.3.2: RCC PLL configuration register (RCC_PLLCFGR),
Section 6.3.23: RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
and Section 6.3.24: RCC PLL configuration register (RCC_PLLSAICFGR).
Updated Section 11.3: AHB interface, Section 11.4.3: SDRAM address
mapping, Section 11.5.4: NOR Flash/PSRAM controller asynchronous
transactions, Section 11.5.6: NOR/PSRAM controller registers,
SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4), FIFO
status and interrupt register (FMC_SR), Common memory space timing
register 2..4 (FMC_PMEM) and Attribute memory space timing registers
(FMC_PATT), SDRAM initialization.
Updated Table 74: Programmable NAND Flash access parameters.
Updated figures 32, 43, 44, 45 and 46 in Section 11.
Updated footnote 5 of Figure 53, and added footnote 2 to Figure 52 and
footnote 1 to Figure 91.
Updated Section 12.5.7: QUADSPI address register (QUADSPI_AR).
Updated Section 13.2: ADC main features and Section 13.13.2: ADC
control register 1 (ADC_CR1).
Updated figures 110, 139, 153 and Input capture mode in Section 16.
Updated Figure 183
, Section 17.4.3: TIMx slave mode control register
(TIMx_SMCR) and Input capture mode in Section 17.
Updated Table 115: TIMx internal trigger connections and Input capture
mode in Section 18.
Updated Figure 238: Watchdog block diagram and Section 21.4: How to
program the watchdog timeout.
Updated Section 22.6.4: RTC initialization and status register (RTC_ISR).
Updated Section 23.7.5: Timing register (FMPI2C_TIMINGR).
Updated Section 24.6.2: I2C Control register 2 (I2C_CR2).
Added Section 25.3: USART implementation.
Updated tables in Section 25.4.4: Fractional baud rate generation.
Updated figures 305, 306, 307 and 308, and their footnotes in
Section 26.3: SPI functional description.
Updated Section 29.1: SDIO main features, Section 29.3: SDIO functional
description, Section 29.8.1: SDIO power control register (SDIO_POWER),
Section 29.8.2: SDIO clock control register (SDIO_CLKCR) and
Section 29.8.4: SDIO command register (SDIO_CMD).
Updated Section 30.7.4: Identifier filtering, CAN filter mode register
(CAN_FM1R), CAN filter scale register (CAN_FS1R), CAN filter FIFO
assignment register (CAN_FFA1R), CAN filter activation register
(CAN_FA1R) and Section 30.9.5: bxCAN register map.
Updated Section 31.15.5: OTG reset register (OTG_GRSTCTL).
Updated Section 33.6.1: MCU device ID code and Section 33.6.3:
Cortex®-M4 with FPU TAP.
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