Revision history RM0390
1320/1328 RM0390 Rev 4
04-Jul-2017 3
Updated Section 1.1: List of abbreviations for registers.
Updated Section 5.4.2: PWR power control/status register (PWR_CSR).
Replaced former Section 9.3.1: General description with Section 9.3.1:
DMA block diagram and Section 9.3.1: DMA block diagram.
Updated Section 11.1: FMC main features, SRAM/NOR-Flash chip-select
timing registers 1..4 (FMC_BTR1..4), Common memory space timing
register 2..4 (FMC_PMEM), Attribute memory space timing registers
(FMC_PATT) and SDRAM Control registers 1,2 (FMC_SDCR1,2).
Updated Table 54: FMC_BCRx bit fields and Table 72: FMC_BCRx bit
fields.
Updated Figure 39: Mode2 write access waveforms and Figure 52: NAND
Flash controller waveforms for common memory access.
Added Section 12.3.2: QUADSPI pins.
Updated Section 12.3.7: QUADSPI memory-mapped mode,
Section 12.3.13: QUADSPI error management and Section 12.5.1:
QUADSPI control register (QUADSPI_CR).
Updated notes in Section 13.13.7: ADC watchdog higher threshold register
(ADC_HTR) and Section 13.13.8: ADC watchdog lower threshold register
(ADC_LTR).
Removed former Section 15.3: DCMI pins and added Section 15.4.1:
DCMI block diagram.
Updated Table 96: DCMI external signals.
Changed D, PIXCLK, HSYNC and VSYNC with, respectively, DCMI_D,
DCMI_HSYNC, DCMI_VSYNC and DCMI_VSYNC in Section 15: Digital
camera interface (DCMI).
Updated FMPI2C master initialization, Section 23.7.2: Control register 2
(FMPI2C_CR2), Section 23.7.3: Own address 1 register (FMPI2C_OAR1),
Section 23.7.4: Own address 2 register (FMPI2C_OAR2) and
Section 23.7.5: Timing register (FMPI2C_TIMINGR).
Updated Figure 247: Slave initialization flowchart.
Updated Section 25.6.1: Status register (USART_SR).
Updated Section 26.1: Introduction,
Section 26.3.7: SPI configuration and
notes in Resetting the SPIx_TXCRC and SPIx_RXCRC values and in
Section 26.7.1: SPI control register 1 (SPI_CR1) (not used in I2S mode).
Added Section 26.6.2: I2S full-duplex.
Updated Section 27.2: SPDIFRX main features, Section 27.3: SPDIFRX
functional description, Section 27.5.1: Control register (SPDIFRX_CR) and
Section 27.5.3: Status register (SPDIFRX_SR).
Added Section 56.3.11: Symbol clock generation, Section 27.3.10: DMA
Interface, Section 56.5.10: SPDIFRX version register (SPDIFRX_VERR),
Section 56.5.11: SPDIFRX identification register (SPDIFRX_IPIDR) and
Section 56.5.12: SPDIFRX size identification register (SPDIFRX_SIDR).
Updated Table 170: SPDIFRX interface register map and reset values.
Table 254. Document revision history (continued)
Date Revision Changes
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