RM0390 Rev 4 1321/1328
RM0390 Revision history
1323
04-Jul-2017
3
cont’d
Added Section 28.3.2: SAI pins and internal signals and updated
Section 1.4.9: SAI clock generator, Section 28.3.9: Internal FIFOs,
Section 28.5.1: Global configuration register (SAI_GCR), Section 28.5.2:
Configuration register 1 (SAI_ACR1 / SAI_BCR1).
Updated Figure 354: SAI functional block diagram and Figure 360: Audio
block clock generator overview.
Updated Table 174: Example of possible audio frequency sampling range
and Table 178: SAI interrupt sources.
Updated Section 31.1: Introduction, Section 31.2.3: Peripheral-mode
features, Section 31.9: OTG low-power modes, Section 31.11.3: FIFO
RAM allocation, Section 31.15.1: OTG control and status register
(OTG_GOTGCTL), Section 31.15.3: OTG AHB configuration register
(OTG_GAHBCFG), Section 31.15.4: OTG USB configuration register
(OTG_GUSBCFG), Section 31.15.5: OTG reset register
(OTG_GRSTCTL), Section 31.15.6: OTG core interrupt register
(OTG_GINTSTS), Section 31.15.9: OTG receive FIFO size register
(OTG_GRXFSIZ), Section 31.15.11: OTG non-periodic transmit
FIFO/queue status register (OTG_HNPTXSTS), Section 31.15.12: OTG
general core configuration register (OTG_GCCFG), Section 31.15.16:
OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx)
(x = 1..5[FS] /8[HS], where x is the FIFO number), Section 31.15.36: OTG
device OUT endpoint common interrupt mask register (OTG_DOEPMSK),
Section 31.15.48: OTG device IN endpoint x control register
(OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint number),
Section 31.15.58: OTG device OUT endpoint x control register
(OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number),
Section 31.15.49: OTG device IN endpoint x interrupt register
(OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number),
Section 31.15.55: OTG device OUT endpoint x interrupt register
(OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number),
Section 31.15.53: OTG device IN endpoint x transfer size register
(OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x = endpoint number),
Section 31.15.52: OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint number),
Section 31.15.59: OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number),
Section 31.16.3: Device initialization, Section 31.16.4: DMA mode,
Section 31.16.5: Host programming model and Section 31.16.6: Device
programming model.
Added Section 31.15.14: OTG core LPM configuration register
(OTG_GLPMCFG) and Section 31.15.51: OTG device IN endpoint x DMA
address register (OTG_DIEPDMAx) (x = 0..8, where x = endpoint number).
Added Table 216: OTG_HS speeds supported and Table 217: OTG_FS
speeds supported.
Updated Table 223: Core global control and status registers (CSRs),
Table 225: Device-mode control and status registers and Tabl e 23 1:
OTG_FS/OTG_HS register map and reset values.
Updated Section 32.1: Introduction.
Added Section 32.3.2: HDMI-CEC block diagram.
Table 254. Document revision history (continued)
Date Revision Changes
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