Revision history RM0390
1322/1328 RM0390 Rev 4
12-Feb-2018 4
Updated Introduction and Section 1.1: List of abbreviations for registers.
Updated Section 2.2.1: Introduction and Section 2.2.2: Memory map and
register boundary addresses, and added Figure 2: Memory map.
Updated Section 5.4.2: PWR power control/status register (PWR_CSR).
Updated Section 9.1: DMA introduction, Section 9.2: DMA main features.
Updated Section 12.5.4: QUADSPI flag clear register (QUADSPI_FCR).
Updated Section 15.7.6: DCMI interrupt clear register (DCMI_ICR).
Updated Section 23.2: FMPI2C main features, Section 23.4.1: FMPI2C
block diagram, Section 23.4.10: SMBus specific features, Section 23.6:
FMPI2C interrupts and Section 23.7.9: PEC register (FMPI2C_PECR).
Updated Table 127: STM32F446xx FMPI2C implementation and
Figure 241: FMPI2C block diagram.
Added Table 132: Examples of timings settings for fI2CCLK = 16 MHz and
Table 131: Examples of timing settings for fI2CCLK = 8 MHz.
Updated Section 26.1: Introduction and Section 26.1: Introduction.
Updated Section 27.3: SPDIFRX functional description, Section 27.3.6:
Data reception management and Section 27.5.1: Control register
(SPDIFRX_CR).
Removed former Section 27.3.10: Symbol clock generation,
Section 56.5.10: SPDIFRX version register (SPDIFRX_VERR),
Section 56.5.11: SPDIFRX identification register (SPDIFRX_IPIDR) and
Section 56.5.12: SPDIFRX size identification register (SPDIFRX_SIDR).
Updated Table 170: SPDIFRX interface register map and reset values.
Updated Frame synchronization polarity, Clock generator programming in
SPDIF generator mode, Anticipated frame synchronization detection
(AFSDET), Wrong clock configuration in master mode (with NODIV = 0),
Section 28.3.14: Disabling the SAI and Section 28.5.2: Configuration
register 1 (SAI_ACR1 / SAI_BCR1).
Updated Table 171: SAI internal input/output signals, Table 172: SAI
input/output pins and Table 179: SAI register map and reset values.
Updated Section 30.2: bxCAN main features, Section 30.3.4: Acceptance
filters, Section 30.6: Behavior in debug mode and Section 30.9.4: CAN
filter registers.
Updated Figure 394: Filtering mechanism - example, Figure 396: Bit timing
and Figure 398: Event flags and interrupt generation.
Updated Figure 400: OTG full-speed block diagram, Figure 401: OTG
high-speed block diagram, Figure 406: Updating OTG_HFIR dynamically
(RLDCTRL = 0), Figure 409: Interrupt hierarchy and its footnote.
Updated Table 223: Core global control and status registers (CSRs),
Table 224: Host-mode control and status registers (CSRs), Table 225:
Device-mode control and status registers, Table 227: Power and clock
gating control and status registers, Table 231: OTG_FS/OTG_HS register
map and reset values.
Removed former Section 31.4.6: External Full-speed OTG PHY using the
I2C interface, Section 31.15.12: OTG I2C access register
(OTG_GI2CCTL) and former footnote 1 from Figure 404.
Added Table 218: OTG implementation for STM32F446xx, Table 219:
OTG_FS input/output pins and Table 220: OTG_HS input/output pins.
Table 254. Document revision history (continued)
Date Revision Changes
To Next Page
Loading...
Need help?
General
