RM0390 Rev 4 1323/1328
RM0390 Revision history
1323
12-Feb-2018
4
cont’d
Updated Section 31.1: Introduction, Section 31.2.1: General features,
Section 31.3: OTG Implementation, Section 31.4.3: OTG core,
Section 31.4.4: Full-speed OTG PHY, Section 31.7: USB host,
Section 31.2.2: Host-mode features, Section 31.9: OTG low-power modes,
Section 31.15.1: OTG control and status register (OTG_GOTGCTL),
Section 31.15.3: OTG AHB configuration register (OTG_GAHBCFG),
Section 31.15.4: OTG USB configuration register (OTG_GUSBCFG),
Section 31.15.7: OTG interrupt mask register (OTG_GINTMSK)
Section 31.15.8: OTG receive status debug read/OTG status read and pop
registers (OTG_GRXSTSR/OTG_GRXSTSP), Section 31.15.12: OTG
general core configuration register (OTG_GCCFG), Section 31.15.13:
OTG core ID register (OTG_CID), Section 31.15.16: OTG device IN
endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5[FS]
/8[HS], where x is the FIFO number), Section 31.15.19: OTG host frame
interval register (OTG_HFIR), Section 31.15.32: OTG device configuration
register (OTG_DCFG), Section 31.15.35: OTG device IN endpoint
common interrupt mask register (OTG_DIEPMSK), Section 31.15.36: OTG
device OUT endpoint common interrupt mask register (OTG_DOEPMSK)
and Section 31.15.52: OTG device IN endpoint transmit FIFO status
register (OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint
number).
Added Section 31.4.2: USB OTG pin and internal signals, Section 31.4.2:
USB OTG pin and internal signals, Section 31.15.42: OTG device IN
endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK),
Section 31.15.45: OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) and Section 31.15.46: OTG device each
OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1).
Updated Section 42.1: Unique device ID register (96 bits) and
Section 42.2: Flash memory size register..
Table 254. Document revision history (continued)
Date Revision Changes
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