Flexible memory controller (FMC) RM0390
314/1328 RM0390 Rev 4
Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL
command.
If the Write data FIFO is not empty, all data are sent to the memory before activating the
Self-refresh mode and the BUSY status flag remains set.
In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which
remains low.
The SDRAM device must remain in Self-refresh mode for a minimum period of time of
TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To
guarantee this minimum period, the BUSY status flag remains high after the Self-refresh
activation during a TRAS delay.
As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of
commands to exit from Self-refresh mode. After the memory access, the selected device
remains in Normal mode.
To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target
Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.
Figure 59. Self-refresh mode
02%#(!2'%
3$#,+
3$#+%
4 4 4
4N 4 4
T2!3MIN
#/--!.$
./0
!54/
2%&2%3(
./0OR#/--!.$
).(%2)4
!54/
2%&2%3(
$/-
$/-,$/-5
!!
!!
!
!,,
"!.+3
$ATA;= (I:
T20
0RECHARGEALL
ACTIVEBANKS
%NTER3ELFREFRESHMODE
#,+STABLEPRIORTOEXISTING
3ELFREFRESHMODE
%XIT3ELFREFRESHMODE
RESTARTREFRESHTIMEBASE
T832
-36
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