Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390
716/1328 RM0390 Rev 4
• If the master addresses a 10-bit address slave, transmits data to this slave and then
reads data from the same slave, a master transmission flow must be done first. Then a
repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this
case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Figure 257. 10-bit address read access with HEAD10R=1
Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th
SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the FMPI2C_CR1 register. The
flag is cleared when the FMPI2C_TXDR register is written with the next data byte to be
transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode
must be selected by setting the RELOAD bit in the FMPI2C_CR2 register. In this case,
when NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched
low until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
• When RELOAD=0 and NBYTES data have been transferred:
– In automatic end mode (AUTOEND=1), a STOP is automatically sent.
– In software end mode (AUTOEND=0), the TC flag is set and the SCL line is
stretched low in order to perform software actions:
A RESTART condition can be requested by setting the START bit in the
FMPI2C_CR2 register with the proper slave address configuration, and number of
bytes to be transferred. Setting the START bit clears the TC flag and the START
condition is sent on the bus.
A STOP condition can be requested by setting the STOP bit in the FMPI2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
• If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically
sent after the NACK reception. the NACKF flag is set in the FMPI2C_ISR register, and
an interrupt is generated if the NACKIE bit is set.
D^ϭϵϴϮϯsϭ
'$7$'$7$
6ODYHDGGUHVV
QGE\WH
6ODYHDGGUHVV
VWELWV
6U
$$
5:
6ODYHDGGUHVV
VWELWV
6 $
;;
;;
:ULWH
5HDG
'$7$ $ 3$'$7$$
$$5:
To Next Page
Loading...
Need help?
General
