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Reset and clock control (RCC) RM0390

152/1328 RM0390 Rev 4

Bit 31 Reserved, must be kept at reset value.

Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG HS ULPI clock disabled during Sleep mode

1: USB OTG HS ULPI clock enabled during Sleep mode

Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG HS clock disabled during Sleep mode

1: USB OTG HS clock enabled during Sleep mode

Bits 28:23 Reserved, must be kept at reset value.

Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode

This bit is set and cleared by software.

0: DMA2 clock disabled during Sleep mode

1: DMA2 clock enabled during Sleep mode

Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode

This bit is set and cleared by software.

0: DMA1 clock disabled during Sleep mode

1: DMA1 clock enabled during Sleep mode

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode

This bit is set and cleared by software.

0: Backup SRAM interface clock disabled during Sleep mode

1: Backup SRAM interface clock enabled during Sleep mode

Bit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode

This bit is set and cleared by software.

0: SRAM2 interface clock disabled during Sleep mode

1: SRAM2 interface clock enabled during Sleep mode

Bit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode

This bit is set and cleared by software.

0: SRAM1 interface clock disabled during Sleep mode

1: SRAM1 interface clock enabled during Sleep mode

Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode

This bit is set and cleared by software.

0: Flash interface clock disabled during Sleep mode

1: Flash interface clock enabled during Sleep mode

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 CRCLPEN: CRC clock enable during Sleep mode

This bit is set and cleared by software.

0: CRC clock disabled during Sleep mode

1: CRC clock enabled during Sleep mode

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHLPEN: IO port H clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port H clock disabled during Sleep mode

1: IO port H clock enabled during Sleep mode

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English

ST STM32F446 Series User Manual

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