USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1206/1328 RM0390 Rev 4
request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are
dropped from the request queue when the CHDIS bit in OTG_HCCHARx is set to 1.
Before disabling a channel, the application must ensure that there is at least one free space
available in the non-periodic request queue (when disabling a non-periodic channel) or the
periodic request queue (when disabling a periodic channel). The application can simply
flush the posted requests when the request queue is full (before disabling the channel), by
programming the OTG_HCCHARx register with the CHDIS bit set to 1, and the CHENA bit
cleared to 0.
The application is expected to disable a channel on any of the following conditions:
1. When an STALL, TXERR, BBERR or DTERR interrupt in OTG_HCINTx is received for
an IN or OUT channel. The application must be able to receive other interrupts
(DTERR, Nak, data, TXERR) for the same channel before receiving the halt.
2. When an XFRC interrupt in OTG_HCINTx is received during a non periodic IN transfer
or high-bandwidth interrupt IN transfer
3. When a DISCINT (disconnect device) interrupt in OTG_GINTSTS is received. (The
application is expected to disable all enabled channels).
4. When the application aborts a transfer before normal completion.
Ping protocol
When the OTG_HS host operates in high speed, the application must initiate the ping
protocol when communicating with high-speed bulk or control (data and status stage) OUT
endpoints.The application must initiate the ping protocol when it receives a
NAK/NYET/TXERR interrupt. When the OTG_HS host receives one of the above
responses, it does not continue any transaction for a specific endpoint, drops all posted or
fetched OUT requests (from the request queue), and flushes the corresponding data (from
the transmit FIFO).This is valid in slave mode only. In Slave mode, the application can send
a ping token either by setting the DOPING bit in OTG_HCTSIZx before enabling the channel
or by just writing the OTG_HCTSIZx register with the DOPING bit set when the channel is
already enabled. This enables the OTG_HS host to write a ping request entry to the request
queue. The application must wait for the response to the ping token (a NAK, ACK, or
TXERR interrupt) before continuing the transaction or sending another ping token. The
application can continue the data transaction only after receiving an ACK from the OUT
endpoint for the requested ping. In DMA mode operation, the application does not need to
set the DOPING bit in OTG_HCTSIZx for a NAK/NYET response in case of bulk/control
OUT. The OTG_HS host automatically sets the DOPING bit in OTG_HCTSIZx, and issues
the ping tokens for bulk/control OUT. The OTG_HS host continues sending ping tokens until
it receives an ACK, and then switches automatically to the data transaction.
Operational model
The application must initialize a channel before communicating to the connected device.
This section explains the sequence of operation to be performed for different types of USB
transactions.
• Writing the transmit FIFO
The OTG_FS/OTG_HS host automatically writes an entry (OUT request) to the
periodic/non-periodic request queue, along with the last 32-bit word write of a packet.
The application must ensure that at least one free space is available in the
periodic/non-periodic request queue before starting to write to the transmit FIFO. The
application must always write to the transmit FIFO in 32-bit words. If the packet size is
non-32-bit word aligned, the application must use padding. The OTG_FS/OTG_HS
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