USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1228/1328 RM0390 Rev 4
transfers. The deeper the queue (along with sufficient FIFO size), the more often the
core is able to pipeline non-periodic transfers. If the queue size is small, the core is
able to put in new requests only when the queue space is freed up.
The core’s periodic request queue depth is critical to perform periodic transfers as
scheduled. Select the periodic queue depth, based on the number of periodic transfers
scheduled in a microframe. If the periodic request queue depth is smaller than the
periodic transfers scheduled in a microframe, a frame overrun condition occurs.
• Handling babble conditions
OTG_FS/OTG_HS controller handles two cases of babble: packet babble and port
babble. Packet babble occurs if the device sends more data than the maximum packet
size for the channel. Port babble occurs if the core continues to receive data from the
device at EOF2 (the end of frame 2, which is very close to SOF).
When OTG_FS/OTG_HS controller detects a packet babble, it stops writing data into
the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes
already written data in the Rx buffer and generates a Babble interrupt to the
application.
When OTG_FS/OTG_HS controller detects a port babble, it flushes the Rx FIFO and
disables the port. The core then generates a port disabled interrupt (HPRTINT in
OTG_GINTSTS, PENCHNG in OTG_HPRT). On receiving this interrupt, the
application must determine that this is not due to an overcurrent condition (another
cause of the port disabled interrupt) by checking POCA in OTG_HPRT, then perform a
soft reset. The core does not send any more tokens after it has detected a port babble
condition.
Note: The following paragraphs, ranging from here to the beginning of Section 31.16, and
covering DMA configurations, apply only to USB OTG HS.
• Bulk and control OUT/SETUP transactions in DMA mode
The sequence of operations is as follows:
1. Initialize and enable channel 1 as explained in Section : Channel initialization.
2. The OTG_HS host starts fetching the first packet as soon as the channel is enabled.
For internal DMA mode, the OTG_HS host uses the programmed DMA address to
fetch the packet.
3. After fetching the last 32-bit word of the second (last) packet, the OTG_HS host masks
channel 1 internally for further arbitration.
4. The OTG_HS host generates a CHH interrupt as soon as the last packet is sent.
5. In response to the CHH interrupt, de-allocate the channel for other transfers.
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