USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1240/1328 RM0390 Rev 4
Operational model
SETUP and OUT data transfers:
This section describes the internal data flow and application-level operations during data
OUT transfers and SETUP transactions.
• Packet read
This section describes how to read packets (OUT data and SETUP packets) from the
receive FIFO.
1. On catching an RXFLVL interrupt (OTG_GINTSTS register), the application must read
the receive status pop register (OTG_GRXSTSP).
2. The application can mask the RXFLVL interrupt (in OTG_GINTSTS) by writing to
RXFLVLM = 0 (in OTG_GINTMSK), until it has read the packet from the receive FIFO.
3. If the received packet’s byte count is not 0, the byte count amount of data is popped
from the receive data FIFO and stored in memory. If the received packet byte count is
0, no data is popped from the receive data FIFO.
4. The receive status readout of the packet of FIFO indicates one of the following:
a) Global OUT NAK pattern:
PKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = (0x0),
DPID = (0b00).
These data indicate that the global OUT NAK bit has taken effect.
b) SETUP packet pattern:
PKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num,
DPID = DATA0. These data indicate that a SETUP packet for the specified
endpoint is now available for reading from the receive FIFO.
c) Setup stage done pattern:
PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num,
DPID = (0b00).
These data indicate that the setup stage for the specified endpoint has completed
and the data stage has started. After this entry is popped from the receive FIFO,
the core asserts a setup interrupt on the specified control OUT endpoint.
d) Data OUT packet pattern:
PKTSTS = DataOUT, BCNT = size of the received data OUT packet (0 BCNT
1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual
Data PID.
e) Data transfer completed pattern:
PKTSTS = Data OUT transfer done, BCNT = 0x0, EPNUM = OUT EP Num on
which the data transfer is complete, DPID = (0b00).
These data indicate that an OUT data transfer for the specified OUT endpoint has
completed. After this entry is popped from the receive FIFO, the core asserts a
transfer completed interrupt on the specified OUT endpoint.
5. After the data payload is popped from the receive FIFO, the RXFLVL interrupt
(OTG_GINTSTS) must be unmasked.
6. Steps 1–5 are repeated every time the application detects assertion of the interrupt line
due to RXFLVL in OTG_GINTSTS. Reading an empty receive FIFO can result in
undefined core behavior.
Figure 424 provides a flowchart of the above procedure.
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