HDMI-CEC controller (HDMI-CEC) RM0390
1278/1328 RM0390 Rev 4
Bit 4 BRESTP: Rx-Stop on Bit Rising Error
The BRESTP bit is set and cleared by software.
0: BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.
1: BRE detection stops message reception
Bit 3 RXTOL: Rx-Tolerance
The RXTOL bit is set and cleared by software.
0: Standard tolerance margin:
– Start-Bit, +/- 200 µs rise, +/- 200 µs fall.
– Data-Bit: +/- 200 µs rise. +/- 350 µs fall.
1: Extended Tolerance
– Start-Bit: +/- 400 µs rise, +/- 400 µs fall
– Data-Bit: +/-300 µs rise, +/- 500 µs fall
Bits 2:0 SFT: Signal Free Time
SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods
waited before transmission is ruled by hardware according to the transmission history. In all the other
configurations the SFT number is determined by software.
″ 0x0
– 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission
(ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1)
– 4 Data-Bit periods if CEC is the new bus initiator
– 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1)
″ 0x1: 0.5 nominal data bit periods
″ 0x2: 1.5 nominal data bit periods
″ 0x3: 2.5 nominal data bit periods
″ 0x4: 3.5 nominal data bit periods
″ 0x5: 4.5 nominal data bit periods
″ 0x6: 5.5 nominal data bit periods
″ 0x7: 6.5 nominal data bit periods
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