ST STM32F446 Series User Manual

Power controller (PWR) RM0390
94/1328 RM0390 Rev 4
Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the following functions are available:
• PC14 and PC15 can be used as LSE pins only
• PC13 can be used as the RTC_AF1 pin (refer to Table 24: RTC_AF1 pin for more
details about this pin configuration).
Backup domain access
After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is
protected against possible unwanted write accesses. To enable access to the backup
domain, proceed as follows:
• Access to the RTC and RTC backup registers
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 6.3.13: RCC APB1 peripheral clock enable register
(RCC_APB1ENR))
2. Set the DBP bit in the Section 5.4.1: PWR power control register (PWR_CR) and PWR
power control register (PWR_CR) to enable access to the backup domain
3. Select the RTC clock source: see Section 6.2.8: RTC/AWU clock
4. Enable the RTC clock by programming the RTCEN [15] bit in the Section 6.3.20: RCC
Backup domain control register (RCC_BDCR)
• Access to the backup SRAM
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 6.3.13).
2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the
backup domain
3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1
peripheral clock enable register (RCC_AHB1ENR).
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to .
Backup SRAM
The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit
mode. Its content is retained even in Standby or V
BAT
mode when the low-power backup
regulator is enabled. It can be considered as an internal EEPROM when V
BAT
is always
present.
When the backup domain is supplied by V
DD
(analog switch connected to V
DD
), the backup
SRAM is powered from V
DD
which replaces the V
BAT
power supply to save battery life.
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the backup SRAM is powered by a dedicated low-power regulator. This

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English