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RM0453 Rev 1 1209/1461

RM0453 Universal synchronous/asynchronous receiver transmitter (USART/UART)

1266

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 UDRCF:SPI slave underrun clear flag

Writing 1 to this bit clears the UDRF flag in the USART_ISR register.

Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at

reset value. Refer to Section 35.4: USART implementation on page 1129

Bit 12 EOBCF: End of block clear flag

Writing 1 to this bit clears the EOBF flag in the USART_ISR register.

Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept

at reset value. Refer to Section 35.4: USART implementation on page 1129.

Bit 11 RTOCF: Receiver timeout clear flag

Writing 1 to this bit clears the RTOF flag in the USART_ISR register.

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and

must be kept at reset value. Refer to Section 35.4: USART implementation on

page 1129.

Bit 10 Reserved, must be kept at reset value.

Bit 9 CTSCF: CTS clear flag

Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

Note: If the hardware flow control feature is not supported, this bit is reserved and must be

kept at reset value. Refer to Section 35.4: USART implementation on page 1129.

Bit 8 LBDCF: LIN break detection clear flag

Writing 1 to this bit clears the LBDF flag in the USART_ISR register.

Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer

to Section 35.4: USART implementation on page 1129.

Bit 7 TCBGTCF: Transmission complete before Guard time clear flag

Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.

Bit 6 TCCF: Transmission complete clear flag

Writing 1 to this bit clears the TC flag in the USART_ISR register.

Bit 5 TXFECF: TXFIFO empty clear flag

Writing 1 to this bit clears the TXFE flag in the USART_ISR register.

Bit 4 IDLECF: Idle line detected clear flag

Writing 1 to this bit clears the IDLE flag in the USART_ISR register.

Bit 3 ORECF: Overrun error clear flag

Writing 1 to this bit clears the ORE flag in the USART_ISR register.

Bit 2 NECF: Noise detected clear flag

Writing 1 to this bit clears the NE flag in the USART_ISR register.

Bit 1 FECF: Framing error clear flag

Writing 1 to this bit clears the FE flag in the USART_ISR register.

Bit 0 PECF: Parity error clear flag

Writing 1 to this bit clears the PE flag in the USART_ISR register.

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English

ST STM32WL5 Series User Manual

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ST STM32WL5 Series Specifications

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