Debug support (DBG) RM0453
1352/1461 RM0453 Rev 1
Bit 22 CYCEVTENA: enable for POSTCNT underflow event counter packet generation
0: Disabled
1: Enabled
Bit 21 FOLDEVTENA: enable for folded instruction counter overflow event generation
0: Disabled
1: Enabled
Bit 20 LSUEVTENA: enable for LSU counter overflow event generation
0: Disabled
1: Enabled
Bit 19 SLEEPEVTENA: enable for sleep counter overflow event generation
0: Disabled
1: Enabled
Bit 18 EXCEVTENA: enable for exception overhead counter overflow event generation
0: Disabled
1: Enabled
Bit 17 CPIEVTENA: enable for CPI counter overflow event generation
0: Disabled
1: Enabled
Bit 16 EXCTRCENA: enable for exception trace generation
0: Disabled
1: Enabled
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 PCSAMPLENA: enable for POSTCNT counter used as a timer for periodic PC sample packet
generation
0: Disabled
1: Enabled
Bits 11:10 SYNCTAP[1:0]: synchronization packet counter tap
Selects the position of the synchronization packet counter tap on the CYCCNT counter. This
determines the synchronization packet rate.
0x0: Disabled. No synchronization packets
0x1: Tap at CYCCNT[24]
0x2: Tap at CYCCNT[26]
0x3: Tap at CYCCNT[28]
Bit 9 CYCTAP: Selects the position of the POSTCNT tap on the CYCCNT counter.
0: Tap at CYCCNT[6]
1: Tap at CYCCNT[10]
Bits 8:5 POSTINIT[3:0]: initial value of the POSTCNT counter
Writes to this field are ignored if POSTCNT counter is enabled (CYCEVTENA or
PCSAMPLENA must be reset prior to writing POSTINIT).
Bits 4:1 POSTPRESET[3:0]: Reloads value of the POSTCNT counter.
Bit 0 CYCCNTENA: enable for CYCCNT counter
0: Disabled
1: Enabled
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