Reset and clock control (RCC) RM0453
334/1461 RM0453 Rev 1
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
These bits are set and cleared by software to select the I2C3 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: Reserved
Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection
These bits are set and cleared by software to select the I2C2 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock
11: Reserved
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
These bits are set and cleared by software to select the I2C1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: Reserved
Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection
These bits are set and cleared by software to select the LPUART1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 9:8 SPI2S2SEL[1:0]: SPI2S2 I2S clock source selection
This bit is set and cleared by software to select the SPI2S2 I2S clock source.
00: Reserved
01: PLL “Q” clock (PLLQCLK) selected
10: HSI16 clock selected
11: External input I2S_CKIN selected
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
These bits are set and cleared by software to select the USART1 clock source.
00: PCLK selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
To Next Page
Loading...
