Sun Microsystems Blade 1500 - Page 153

Chapter 7 Power-On Self-Test 7-9
@(#)OBP 4.16.3 2004/11/05 18:29 Sun Blade 1500 (Silver)
Clearing TLBs
Executing Power On Self Test
OpenBoot PROM resets the
system and starts POST.
0>@(#) Sun Blade[TM] 1500 POST 4.16.3 2004/11/05 19:58
POST build version and date is
displayed.
/dat/fw/common-source/firmware_re/post/post-build-
4.16.3/Fiesta/taco/integrated (firmware_re)
POST build path is displayed.
0>Copyright © 2004 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
Copyright and license displayed.
0>Soft Power-on RST thru SW
0>OBP->POST Call with %o0=00001000.01012000.
0>Diag level set to MIN.
0>Verbosity level set to MAX.
0>MFG scrpt mode set NORM
0>I/O port set to TTYA.
CPU0 is acknowledged and POST
configuration is read from
register.
0>Start Selftest.....
0>CPUs present in system: 0
0>Test CPU(s).....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
CPU, I/O bridge, data memory
management unit (DMMU), and
instruction memory management
unit (IMMU) are initialized.
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Scrub and Setup L2 Cache
L2 cache is set up and scrubbed
(data values set to defaults).
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
DMMU is set up.
0>Test Mailbox
0>Scrub Mailbox
Mailbox register is checked and
initialized.
0>CPU Tick and Tick Compare Registers Test
Operation of TICK registers is
verified.
0>CPU Stick and Stick Compare Registers Test
Operation of STICK registers is
verified.
0>Set Timing
Motherboard timing is to be
configured.
0> UltraSPARC[TM] IIIi, Version 3.4
CPU version is identified.
TABLE 7-5 post min max Output Comparison (Continued)
Output Displayed What Is Happening