Appendix C Functional Description C-9
C.3 CPU and Memory
C.3.1 CPU Description
The UltraSPARC IIIi processor is a high-performance, highly integrated superscalar
processor. It is capable of sustained execution of four instructions per cycle, even
with conditional branches and cache misses. Instructions are issued in program
order to multiple functional units, and executed in parallel. Instructions from two
basic blocks are issued in the same group to further increase the number of
instructions executed per cycle.
The UltraSPARC IIIi CPU supports full implementation of the 64-bit SPARC-V9
architecture, a 64-bit virtual address space, and a 43-bit physical address space. The
core instruction set includes graphics instructions that provide the most common
operations used for two-dimensional image processing, two and three-dimensional
graphics, image compression algorithms, and parallel operations on pixel data with
8 and 16-bit components.
C.3.2 Caches
C.3.2.1 L1 Data Cache
■ 64 KBytes
■ Four-way set associative
■ Write-through
■ Nonallocating (no write allocate)
■ Virtually indexed (doesn’t go through D-TLB), physically tagged (goes through
D-TLB)
■ Address aliasing as side effect
■ 32-byte line size, no sub-lines
■ Data and tags are parity protected
■ Not included in L2 cache. Is snooped in parallel with L2
■ Need to flush if alias is created
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