Sun Microsystems Blade 1500 - Page 442

C-10 Sun Blade 1500 Service, Diagnostics, and Troubleshooting Manual • December 2004
C.3.2.2 L1 Instruction Cache
■ 32 KBytes
■ Pseudo four-way set associative
■ Physically indexed (goes through I-TLB), physically tagged (goes through I-TLB)
■ Write invalidate
■ 32-byte line size, no sub-lines
■ Data and tags are parity protected
■ Not included in L2 cache. Is snooped in parallel with L2
■ No flushing is required
C.3.2.3 L1 Prefetch Cache
■ Used by software prefetch instruction and autonomous HW prefetch from L2
■ 2 KBytes
■ Four-way set associative
■ Physically indexed (goes through D-TLB), physically tagged (goes through D-
TLB)
■ Write invalidate
■ 64-byte line size, two 32-byte sub lines
■ Not included in L2 cache. Is snooped in parallel with L2
■ No flushing is required
C.3.2.4 L2 Data Cache
■ 1 MByte
■ Four-way set associative
■ Physically indexed (goes through D-TLB), physically tagged (goes through D-
TLB)
■ Write back, allocating
■ 64-byte line size
■ Data is ECC protected, tag is parity protected
■ L2 tag address able to cache 16 GB of local memory
■ Required flushing for stable storing