Sun Microsystems Blade 1500 - Memory Controller; Memory Block Diagram; C.3.3 Memory Controller

Appendix C Functional Description C-11
C.3.2.5 L2 Write Cache
■ Used to reduce bandwidth to L2 Cache by coalescing and bursting stores to L2
cache
■ 2 KBytes
■ Four-way set associative
■ 64-byte line size, two 32-byte sub-lines
■ Physically indexed (goes through Data Translation Look-aside Buffers (D-TLB)),
physically tagged (goes through D-TLB)
■ Included in L2 cache
■ Required flushing for stable storing
C.3.3 Memory Controller
The memory system consists of the Memory Control Unit (MCU) in the CPU, and
two physical banks (A and B) of DDR-1 Synchronous DRAM memory. Only
registered DIMMS are supported.
Clock buffering with a PLL is provided on the DIMMs. Each physical bank consists
of two 72-bit DDR-1 SDRAM DIMMs. These two DIMMs share an 8-byte data bus
plus ECC data bus. Both physical banks have shared address/control bus. Since each
DIMM could be dual sided (upper/lower banks), there are maximum of four data
loads per physical bank. The cache line is split across the two physical banks. Both
banks are controlled by the memory controller.
Note – DIMMs are always loaded in pairs.
A memory controller pipelines requests, making use of 16 memory banks when fully
loaded.
C.3.4 Memory Block Diagram
FIGURE C-4 shows the memory block diagram for the Sun Blade 1500 workstation.