Appendix C Functional Description C-15
C.4 Internal Interfaces and ASICs
This section discusses system buses, interfaces, and the ASICs that support them on
the motherboard:
■ “JBus Information” on page C-15
■ “JIO Information” on page C-16
■ “PCI Bus Information” on page C-17
■ “M1535D+” on page C-18
■ “BCM5793” on page C-19
■ “Other Buses” on page C-20
C.4.1 JBus Information
JBus is a 128-bit MUX address and data bus running at 200MHz SDR with
approximately 171 DTL signals. JBus is a multidrop with a peak bandwidth of
2.56GB/s@200MHz. JBus can insert a dead cycle between transactions of 2 different
masters if needed. The bus supports two loads — the UltraSPARC IIIi processor and
the JIO I/O bridge.
Key Features
The following are the key features of JBus:
■ Simple SMP protocol that is SPARC-V9 and Sun4u correct, high performance for
1-4 CPUs
■ 128-bit wide bus
■ Full duplex shared multidrop bus up to four loads
■ DTL driver/receiver technology
■ Snoopy MOESI protocol
■ Separate flow-controlled address and data transaction
■ Multiplexed address and data bus
■ Variable snoop return delay using sideband signals (no hard latency or
throughput requirements in the protocols)
■ Distributed arbitration
■ Distributed snoop results stalling for resource management
■ Pushed writes, slit transID based read returns
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