Chapter 7 Power-On Self-Test 7-11
0>Data Bitwalk on Master
CPU data pins are tested.
0> Test Bank 0.
Where found, memory is tested.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to
00000000.40000000.
CPU address pins are tested.
0>Set Mailbox
Mailbox register is set.
0>Final mc1 is b0000026.3e781c61.
Memory control register 1 is set.
0>Setup Final DMMU Entries
Memory is allocated for POST.
0>Post Image Region Scrub
Allocated memory is set to
defaults.
0>Run POST from Memory
POST is transferred to new
memory and executed.
0>Verifying checksum on copied image.
0>The Memory’s CHECKSUM value is 3f81.
0>The Memory’s Content Size value is 68111.
0>Success... Checksum on Memory Validated.
Copied data is verified.
0>FPU Registers and Data Path
0>FPU Move Registers
Floating point unit (FPU) is
checked.
0>FSR Read/Write
FPU status register is checked.
0>FPU Block Register Test
Additional FPU testing is
performed.
0>Scrub Memory
Memory is set to zero.
0>Quick Block Mem Test
0>Quick Test 4194304 bytes at 00000000.00600000
A quick test of memory is made at
a particular address.
0>Flush Caches
Caches are set to zero.
0>XBus SRAM
XBus buffer memory is checked.
0>IO-Bridge SouthBridge Remap Devs
I/O bridge and I/O subsystem
probe for devices.
0>IO-Bridge Tests.....
I/O bridge is checked.
0>JBUS quick check
0> to IO-bridge_1
JBus communication with I/O
bridge is checked.
0>IO-Bridge unit 1 sram test
32K scratch pad SRAM is checked.
0>IO-Bridge unit 1 reg test
I/O bridge registers are checked.
0>IO-Bridge unit 1 mem test
I/O bridge memory is checked.
0>IO-Bridge unit 1 PCI id test
I/O bridge PCI buses are checked.
TABLE 7-5 post min max Output Comparison (Continued)
Output Displayed What Is Happening
To Next Page
Loading...
