Sun Microsystems Blade 1500 - Page 159

Chapter 7 Power-On Self-Test 7-15
0>MB: Part-Dash-Rev#: 3753187-01-Serial#:
Motherboard part number and
serial number is read from FRU
ID.
0>CPU0 DIMM 0:
0>Part#: M3 12L6420ETS-CA2 Serial#: 4505079a Date Code: 0347
Rev#: 5345
0>CPU0 DIMM 1:
0>Part#: M3 12L6420ETS-CA2 Serial#: 45040799 Date Code: 0347
Rev#: 5345
DIMM part numbers, serial
numbers, date codes, and
revisions are read from FRU IDs.
0>Set CPU/System Speed
0>CPU Config Jumper = 00000004
Jumpers for CPU and JBus
frequency are read.
0>Init Memory.....
Memory is initialized
0>Probe Dimms
Presence of DIMMs is checked.
0>Init Mem Controller Regs
Memory controller registers are
initialized.
0>Set JBUS config reg
JBus frequency register is set.
0>IO-Bridge unit 1 init test
I/O bridge chip is initialized.
0>Do PLL reset
Phase locked loop (PLL) is reset.
0>Setting timing to 10:1 12:1, system frequency 160 MHz, CPU
frequency 1500 MHz
Reconfigured frequencies are
displayed.
0>Soft Power-on RST thru SW
Soft reset.
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
Initializations and set ups are
repeated.
0>Timing is 10:1 12:1, sys 160 MHz, CPU 1500 MHz, mem 133 MHz.
New timing ratios and frequencies
are displayed.
0> UltraSPARC[TM] IIIi, Version 3.3
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Sequence
0>IO-Bridge unit 1 init test
Repeated initialization continues.
TABLE 7-7 post max max Output Comparison (Continued)
Output Displayed What Is Happening