Chapter 7 Power-On Self-Test 7-17
0>8k DMMU TLB 0 Data
0>8k DMMU TLB 1 Data
0>8k DMMU TLB 0 Tags
0>8k DMMU TLB 1 Tags
0>8k IMMU TLB Data
0>8k IMMU TLB Tags
Translation look-aside buffers
(TLB) are tested for data and
instruction buffers.
0>FPU Registers and Data Path
0>FPU Move Registers
Floating point unit (FPU) is
checked.
0>FSR Read/Write
FPU status register is checked.
0>FPU Block Register Test
0>FPU Branch Instructions
0>FPU Functional Test
Additional FPU testing is
performed.
0>Scrub Memory
Memory is set to zero.
0>Flush Caches
Caches are set to zero.
0>Functional CPU Tests.....
CPU is checked.
0>XBus SRAM
XBus buffer memory is checked.
0>IO-Bridge SouthBridge Remap Devs
I/O bridge and I/O subsystem
probe for devices.
0>IO-Bridge Tests.....
I/O bridge is checked.
0>JBUS quick check
0> to IO-bridge_1
JBus communication with I/O
bridge is checked.
0>IO-Bridge unit 1 sram test
32K scratch pad SRAM is checked.
0>IO-Bridge unit 1 reg test
I/O bridge registers are checked.
0>IO-Bridge unit 1 mem test
I/O bridge memory is checked.
0>IO-Bridge unit 1 PCI id test
I/O bridge PCI buses are checked.
0>IO-Bridge unit 1 interrupt test
I/O bridge interrupts are checked.
0>Print Mem Config
Memory configuration is to be
displayed.
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
Cache status is displayed.
0>Memory interleave set to 0
0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.
4 megabyte portion of memory is
scrubbed and tested.
0>Block Memory
Memory is checked again.
TABLE 7-7 post max max Output Comparison (Continued)
Output Displayed What Is Happening
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